From you diagram it looks like you are connected and MC Lag to two separate CE devices so I see two possiblilities and both present issues you note.
If the two devices are separate you are connection a LAG to non-LAG ports on two devices.
If the two devices also have MC-LAG you will have issues with the two MC setups communicating which is the Active link to each other.
In the typical design we connection MC-LAG on one side to single chassis AE bundle on each other device. 4 ports on each side then for the redundancy.
See the typical examples in the MX Series chapter overview of MC LAG here.
https://www.safaribooksonline.com/library/view/juniper-mx-series/9781449358143/ch08s03.html